| Publication date | Communities | Collections | Article title | Author(s) | Journal/Conference |
|---|---|---|---|---|---|
| 1 Sep 2015 | SERC | Institute of Microelectronics | Stress Analysis and Design Optimization for Low-k Chip With Cu Pillar Interconnection | Lin Jong-Kai, Au Keng Yuen, Hsiao Hsiang-Yao, Zhang Xiaowu, Che Fa Xing | IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY |