| Publication date | Communities | Collections | Article title | Author(s) | Journal/Conference |
|---|---|---|---|---|---|
| 13 May 2015 | SERC | Institute of Microelectronics | Design and Optimization of Wafer-Level Compression Molding Process for One Chip Plus Multiple Decaps | Bu Lin, Ho Siowling, S.D. Velez, Long Lau Boon, Jung Booyang, Chai Taichong, Zhang Xiaowu | Components, Packaging and Manufacturing Technology, IEEE Transactions on |